Part Number Hot Search : 
CE12022 SBL20100 93NJ10RE CW0603 HT27C010 SRP350D 471ME 2SC5141
Product Description
Full Text Search
 

To Download ICS844020-45 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
  femtoclock? crystal-to-lvds/ lvcmos frequency synthesizer ICS844020-45 idt ? / ics ? lvds/lvcmos frequency synthesizer 1 ICS844020-45 rev a june 14, 2006 preliminary g eneral d escription the ICS844020-45 is a 20 output synthesizer optimized to generate gigabit and 10 gigabit ethernet clocks and is a member of the hipercloc ks? f amily of high performance clock solutions from ics. using a 25mhz 18pf parallel resonant crystal, the device will generate 156.25, 125mhz, 25mhz and 3.90625mhz clocks with mixed lvds and lvttl output logic. the ICS844020-45 uses ics? 3rd generation low phase noise vco technology and can achieve <1ps typical rms phase jitter, easily meeting ethernet jitter requirements. the ICS844020-45 is packaged in a 64-pin tqfp package with exposed pad for optimum thermal performance. f eatures ? sixteen differential lvds outputs at 125mhz one differential lvds output at 156.25mhz one lvcmos/lvttl single-ended output at 125mhz one lvcmos/lvttl single-ended output at 25mhz one lvcmos/lvttl single-ended output at 3.90625mhz ? crystal oscillator interface ? vco range: 490mhz - 680mhz ? rms phase jitter @ 125mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.4ps (typical) ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.37ps (typical) ? full 2.5v operating supply ? 0c to 70c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages hiperclocks? ic s p in a ssignment 64-lead tqfp, epad 10mm x 10mm x 1.0mm package body y package top view 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ICS844020-45 gnd nq14 q14 v dd nq13 q13 gnd nq12 q12 v dd nq11 q11 gnd nq10 q10 v dd gnd q0 nq0 v dd q1 nq1 gnd q2 nq2 v dd q3 nq3 gnd q4 nq4 v dd v dd q5 nq5 gnd q6 nq6 v dd q7 nq7 gnd q8 nq8 v dd q9 nq9 gnd xtal_in xtal_out gnd gnd q19 v ddo q18 q17 gnd nq16 q16 v dd nq15 q15 gnd v dda osc phase detector vco 490-680mhz 25 5 4 160 q0 nq0 q15 nq15 q17 nq16 q16 q18 q19 xtal_in xtal_out 25mhz b lock d iagram 125mhz 156.25mhz 3.90625mhz 25mhz the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specifications w ithout notice.
idt ? / ics ? lvds/lvcmos frequency synthesizer 2 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary t able 2. p in c haracteristics t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d , 6 2 , 0 2 , 3 1 , 7 , 1 , 8 4 , 2 4 , 6 3 , 2 3 2 6 , 1 6 , 6 5 , 0 5 d n gr e w o p. d n u o r g y l p p u s r e w o p 3 , 2 6 , 5 9 , 8 2 1 , 1 1 5 1 , 4 1 9 1 , 8 1 2 2 , 1 2 5 2 , 4 2 8 2 , 7 2 1 3 , 0 3 5 3 , 4 3 8 3 , 7 3 1 4 , 0 4 4 4 , 3 4 7 4 , 6 4 2 5 , 1 5 5 5 , 4 5 0 q n , 0 q 1 q n , 1 q 2 q n , 2 q 3 q n , 3 q 4 q n , 4 q 5 q n , 5 q 6 q n , 6 q 7 q n , 7 q 8 q n , 8 q 9 q n , 9 q 0 1 q n , 0 1 q 1 1 q n , 1 1 q 2 1 q n , 2 1 q 3 1 q n , 3 1 q 4 1 q n , 4 1 q 5 1 q n , 5 1 q 6 1 q n , 6 1 q t u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o k c o l c l a i t n e r e f f i d , 7 1 , 6 1 , 0 1 , 4 , 9 3 , 3 3 , 9 2 , 3 2 3 5 , 5 4 v d d r e w o p. s n i p y l p p u s r e w o p e r o c 9 4v a d d r e w o p. n i p y l p p u s g o l a n a 0 6 , 8 5 , 7 59 1 q , 8 1 q , 7 1 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o k c o l c d e d n e - e l g n i s 9 5v o d d r e w o p. s t u p t u o s o m c v l r o f n i p y l p p u s r e w o p t u p t u o 4 6 , 3 6 , t u o _ l a t x n i _ l a t x t u p n i . t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p n i e h t s i n i _ l a t x l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p d b tf p r t u o e c n a d e p m i t u p t u o 57 2 1 ?
idt ? / ics ? lvds/lvcmos frequency synthesizer 3 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvcmos) -0.5v to v dd + 0.5v outputs, i o (lvds) contin uous current 10ma surge current 15ma operating temperature range, t a -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 22.3c/w (0 lfpm) note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifi- cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. t able 3b. lvcmos/lvttl dc c haracteristics , v dd = v dda = v ddo = 2.5v 5%,t a = 0c to 70c t able 3a. p ower s upply dc c haracteristics , v dd = v dda = v ddo = 2.5v 5%,t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a d d e g a t l o v y l p p u s g o l a n av d d i ? a d d 0 1 * ? 5 . 2v d d v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p d b ta m i a d d t n e r r u c y l p p u s g o l a n a d b ta m i o d d t n e r r u c y l p p u s t u p t u o d b ta m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u o9 1 q : 7 1 q v o d d =v 5 2 6 . 2% 5 8 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o9 1 q : 7 1 q v o d d =v 5 2 6 . 2% 5 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o d d , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . m a r g a i d t i u c r i c t s e t d a o l t u p t u o
idt ? / ics ? lvds/lvcmos frequency synthesizer 4 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary t able 5. ac c haracteristics , v dd = v dda = v ddo = 2.5v 5%,t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d d b tv m ? v d o v d o e g n a h c e d u t i n g a m d b tv m v s o e g a t l o v t e s f f o d b tv ? v s o v s o e g n a h c e d u t i n g a m d b tv m t able 3c. lvds dc c haracteristics , v dd = v dda = 2.5v 5%,t a = 0c to 70c t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 ? e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o t u p t u o y c n e u q e r f 5 1 : 0 q n / 5 1 : 0 q5 2 1z h m 7 1 q5 2 1z h m 6 1 q n / 6 1 q5 2 . 6 5 1z h m 8 1 q5 2 6 0 9 . 3z h m 9 1 q5 2z h m t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o d b ts p t ) ? ( t i j r e t t i j e s a h p s m r ; ) m o d n a r ( 3 e t o n 5 1 : 0 q n / 5 1 : 0 q) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 5 2 10 4 . 0s p 6 1 q n / 6 1 q , z h m 5 2 . 6 5 1 ) z h m 0 2 - z h m 5 7 8 . 1 ( 7 3 . 0s p t r t / f t u p t u o e m i t l l a f / e s i r 5 1 : 0 q n / 5 1 : 0 q% 0 8 o t % 0 2 , z h m 5 2 15 5 . 0s n 6 1 q n : 6 1 q% 0 8 o t % 0 2 , z h m 5 2 . 6 5 10 0 2s p c d o t u p t u o e l c y c y t u d 5 1 : 0 q n / 5 1 : 0 qz h m 5 2 15 45 5% 6 1 q n / 6 1 qz h m 5 2 . 6 5 10 40 6% . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n v t a d e r u s a e m o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n . s t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 3 e t o n
idt ? / ics ? lvds/lvcmos frequency synthesizer 5 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary 2.5v lvds o utput l oad ac t est c ircuit 2.5v lvcmos o utput l oad ac t est c ircuit lvcmos o utput r ise /f all t ime lvcmos o utput s kew lv d s o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v od p arameter m easurement i nformation lvds o utput s kew scope qx nqx lv d s 2.5v5% power supply +? float gnd scope qx lvcmos 1.25v5% -1.25v5% v dd , v ddo gnd 1.25v5% t sk(o) v ddo 2 v ddo 2 qx qy t sk(o) qx qy clock outputs 20% 80% 80% 20% t r t f nqx nqy v dda v dd , v ddo v dda
idt ? / ics ? lvds/lvcmos frequency synthesizer 6 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary rms p hase j itter lvds o utput d uty c ycle /p ulse w idth /p eriod lvcmos o utput d uty c ycle /p ulse w idth /p eriod phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t pw t period t pw t period odc = x 100% nq0:nq16 t period t pw t period odc = v ddo 2 x 100% t pw q17:q19 q0:q16
idt ? / ics ? lvds/lvcmos frequency synthesizer 7 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary 10 100 1k 10k 100k 1m 10m 100m 10 100 1k 10k 100k 1m 10m 100m t ypical p hase n oise at 125mh z ( lvds ) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.40ps (typical) o ffset f requency (h z ) n oise p ower dbc hz ? ? ? 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.37ps (typical) o ffset f requency (h z ) n oise p ower dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 ? ? ? t ypical p hase n oise at 156.25mh z ( lvds ) ethernet filter raw phase noise data phase noise result by adding ethernet filter to raw data phase noise result by adding ethernet filter to raw data raw phase noise data ethernet filter
idt ? / ics ? lvds/lvcmos frequency synthesizer 8 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS844020-45 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 ? resistor along with a 10f and a .01 f bypass capacitor should be connected to each v dda . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 ? v dda 10 f .01 f 2.5v .01 f v dd c rystal i nput i nterface the ICS844020-45 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below figure 2. c rystal i npu t i nterface were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. ics84332 xtal_in xtal_out x1 18pf parallel cry stal c2 22p c1 22p
idt ? / ics ? lvds/lvcmos frequency synthesizer 9 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary o utputs : lvcmos o utput : all unused lvcmos output can be left floating. there should be no trace attached. lvds o utput all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. r ecommendations for u nused o utput p ins lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac couple capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output figure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xtal _i n xtal _ou t .1uf rs
idt ? / ics ? lvds/lvcmos frequency synthesizer 10 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary transmission line environment. for buffer with multiple ldvs driver, it is recommended to terminate the unused outputs. 2.5v lvds d river t ermination figure 4 shows a typical termination for lvds driver in characteristic impedance of 100 ? differential (50 ? single) f igure 4. t ypical lvds d river t ermination 2.5v 100 ohm differential transmission line 2.5v lvds_driv er r1 100 + - 100 ? ? ? ? ? differential transmission line exposed pad expose metal pad (ground pad) ground plane solder signal trace signal trace therm al via solder m ask f igure 5. p.c. b oard for e xposed p ad t hermal r elease p ath e xample t hermal r elease p ath the expose metal pad provides heat transfer from the device to the p.c. board. the expose metal pad is ground pad connected to ground plane through thermal via. the exposed pad on the device to the exposed metal pad on the pcb is contacted through solder as shown in figure 5. for further information, please refer to the application note on surface mount assembly of amkor?s thermally /electrically enhance leadframe base package, amkor technology.
idt ? / ics ? lvds/lvcmos frequency synthesizer 12 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary the ics logo is a registered trademark, and hip erclocks and f emto c locks are trademarks of integrated circuit systems, inc. all other trademarks are the property of their respective owners and may be registered in certain jurisdictions. r eliability i nformation t ransistor c ount the transistor count for ICS844020-45 is: 1782 t able 6.  ja vs . a ir f low t able for 64 l ead tqfp, e-p ad      ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 22.3c/w 17.2c/w 15.1c/w
idt ? / ics ? lvds/lvcmos frequency synthesizer 12 ICS844020-45 rev a june 14, 2006 ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are i mplied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics prod uct for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 5 4 - y a 0 2 0 4 4 8 s c i5 4 - y a 0 2 0 4 4 8 s c id a p - e , p f q t d a e l 4 6y a r tc 0 7 o t c 0 t 5 4 - y a 0 2 0 4 4 8 s c i5 4 - y a 0 2 0 4 4 8 s c id a p - e , p f q t d a e l 4 6l e e r & e p a t 0 0 5c 0 7 o t c 0 f l 5 4 - y a 0 2 0 4 4 8 s c id b td a p - e , p f q t " e e r f - d a e l " d a e l 4 6y a r tc 0 7 o t c 0 t f l 5 4 - y a 0 2 0 4 4 8 s c id b td a p - e , p f q t " e e r f - d a e l " d a e l 4 6l e e r & e p a t 0 0 5c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n the ics logo is a registered trademark, and hip erclocks and f emto c locks are trademarks of integrated circuit systems, inc. all other trademarks are the property of their respective owners and may be registered in certain jurisdictions.
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ICS844020-45 femtoclock? crystal-to-lvds/l vcmos frequency synthesizer preliminary


▲Up To Search▲   

 
Price & Availability of ICS844020-45

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X